Examples of conventional electron emitting devices of the type to which the present invention relates are disclosed in U.S. Pat. Nos. 3,755,704; 3,812,559, 4,857,161; 4,940,916; 5,194,780 and 5,225,820. The disclosures of those patents are incorporated herein by reference.
A typical such structure, embodied as an electron emitter of an FED (field emission device) flat-panel image display device as described by Meyer in U.S. Pat. No. 5,194,780, is shown in FIGS. 1-5. Such device includes an electron emitter plate 10 spaced across a vacuum gap from an anode plate 11 (FIG. 1). Emitter plate 10 comprises a cathode electrode having a plurality of cellular arrays 12 of n x m electrically conductive microtips 14 formed on a resistive layer 15, within respective mesh spacings 16 (FIG. 2) of a conductive layer mesh structure 18 patterned in stripes 19 (referred to as "columns") (FIG. 5) on an upper surface of an electrically insulating (typically glass) substrate 20 overlaid with a thin silicon dioxide (SiO.sub.2) film 21. An extraction (or gate) electrode 22 (FIGS. 1-3) comprises an electrically conductive layer of cross-stripes 24 (referred to as "rows") (FIG. 5) deposited on an insulating layer 25 which serves to insulate electrode 22 and space it from the resistive and conductive layers 15, 18. Microtips 14 are in the shape of cones which are formed within apertures 26 through conductive layer 22 and concentric cavities 41 of insulating layer 25. The microtips 14 are formed utilizing a variation of the self-alignment microtip formation technique described in U.S. Pat. No. 3,755,704, wherein apertures 26 and cavities 41 are etched after deposition of layers 22, 25 and wherein a respective microtip 14 is formed within each aperture 26 and cavity 41. The relative parameters of microtips 14, insulating layer 25 and conductive layer 22 are chosen to place the apex of each microtip 14 generally at the level of layer 22 (FIG. 1). Electrode 22 is patterned to form aperture islands or pads 27 centrally of the mesh spacings 16 in the vicinity of microtip arrays 12, and to remove cross-shaped areas 28 (FIG. 3) over the intersecting conductive strips which form the mesh structure of conductor 18. Bridging strips 29 of electrode 22 are left for electrically interconnecting pads 27 of the same row cross-stripe 24.
Anode plate 11 (FIG. 1) comprises an electrically conductive layer of material 31 deposited on a transparent insulating (typically glass) substrate 32, which is positioned facing extraction electrode 22. The conductive layer 31 is deposited on an inside surface 33 of substrate 32, directly facing gate electrode 22. Conductive layer 31 is typically a transparent conductive material, such as indium-tin oxide (ITO). Anode plate 11 also comprises a phosphor coating 34, deposited over the conductive layer 31, so as to be directly facing and immediately adjacent extraction electrode 22.
In accordance with conventional teachings, groupings of the microtip cellular arrays 12 in mesh spacings 16 corresponding to a particular column-row image pixel location can be energized by applying a negative potential to a selected column stripe 19 (FIG. 5) of cathode mesh structure 18 relative to a selected row cross-stripe 24 of extraction electrode 22, via a voltage source 35, thereby inducing an electric field which draws electrons from the associated subpixel pluralities of n x m microtips 14. The freed electrons are accelerated toward the anode plate 11 which is positively biased by a substantially larger positive voltage applied relative to extraction electrode 22, via the same or a different voltage source 35. Energy from the electrons emitted by the energized microtips 14 and attracted to the anode electrode 31 is transferred to particles of the phosphor coating 34, resulting in luminescence. Electron charge is transferred from phosphor coating 34 to conductive layer 31, completing the electrical circuit to voltage source 35.
The various column-row intersections of stripes 19 of cathode mesh structure 18 and cross-stripes 24 of extraction electrode 22 are matrix-addressed to provide sequential (typically, row-at-a-time) pixel illumination of corresponding phosphor areas, to develop an image viewable to a viewer 36 looking at the front or outside surface 37 of the plate 11. However, even with row-at-a-time addressing, the per pixel addressing duty factor is small. For example, the pixel dwell time (fraction of frame time available to excite each pixel) for row-at-a-time addressing in a 640.times.480 pixel color display refreshed at 60 frames per second (180 RGB color fields per second), is only about 8-10 microseconds per row. This means that for pulsewidth modulated gray scale control, where the dwell time per pixel is further divided into as many as 64 dwell time subintervals, column voltage switching during row "on" times occurs at the rate of about once every 30-40 nanoseconds. At such high switching rates, total gate-to-cathode capacitance for the column stripes 19 becomes a significant factor in the RC time constant and has a predominant adverse influence on the 1/2CV.sup.2 power consumption factor. Some reduction in capacitance is achieved through the described patterning of gate electrode 22, wherein removal of gate electrode from areas 28 reduces capacitance away from the microtips. There remains, however, a pressing need to reduce the column gate-to-cathode capacitance even more in such field effect devices.
Spindt, et al., U.S. Pat. No. 3,812,559 (see FIG. 9 of the '559 patent) illustrates a conventional microtip emission cathode structure wherein a gate electrode is supported only at its periphery. This reduces gate-to-cathode capacitance due to the elimination of most of the gate-supporting dielectric material present in structures such as that of Meyer '780, which have insulating material 25 completely surrounding each microtip 14. The '559 structure has no supports except at the periphery of the entire gate electrode and has the advantage of reducing capacitance especially for high frequency (viz. microwave frequency) operations wherein gate-to-cathode capacitance has particularly adverse consequences. The Spindt '559 structure is, however, subject to several problems. First, except for very small structures, the lack of any support except at the periphery can lead to excess bouncing or vibration of the gate electrode, similar to vibrations encountered by a peripherally supported membrane. This so-called "trampoline" effect can lead to structure failure and undesirable variations of gate-to-cathode current flow. The large unsupported central region is also subject to other problems. In assembly of a display structure, glass balls or other spacers acting between the anode and cathode plates may cause unwanted physical deformation and even destruction of an unsupported gate. Also, during fabrication, surface tension of etching liquids used in wet etching steps (such as for removal of a sacrificial Ni layer) can cause the unsupported structure to break when the liquids are recovered. The unsupported gate region may also be subject to distortion due to electrical attraction between the positively charged gate and the negatively charged cathode.